SIMD within a register on linear feedback shift registers

Abstract

Linear feedback shift registers (LFSRs) are used throughout a subset of cryptography. They have long been deployed as a means to generate a pseudo-random number stream. The random number generation provided by the LFSRs has been utilized in stream ciphers ranging from consumer to military grade. For example GSM privacy relies on the A5/1 stream cipher which in turn relies on LFSRs to generate the keystream. They are deployed because they are easy to construct, yet still provide strong cryptographic properties. The scope of this project is to speed up the simulation of LFSRs. The method of speeding up LFSRs is to use parallel operations to operate on multiple LFSRs at once. This is accomplished by using a method of SIMD. The method is SIMD within a register (SWAR). SWAR uses general purpose machine registers (eg. rax on an x86_64 machine). This means that 64 LFSRs can be simulated at once with one machine register using SWAR. This has the trade-off of latency vs throughput.